PXS20RM Datasheet, PDF (177/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

9.3.13 Channel Data Registers (CDRn)
Analog-to-Digital Converter (ADC)
Address: See Table 9-2.
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R 0 0 0 0 0 0 0 0 0 0 0 0 _{VA OVE RESULT}
W
LID RW
[0:1]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
CDATA
W
(MCR[WLSIDE] = 0)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CDATA
0000
W
(MCR[WLSIDE] = 1)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-20. Channel Data Register n (CDRn)
Table 9-23. CDRn field descriptions
Field
Description
VALID Used to notify when the data is valid (a new value has been written). It is automatically cleared when
data is read.
OVERW
Overwrite data
This bit signals that the previous converted data has been overwritten by a new conversion. This
functionality depends on the value of MCR[OWREN]:
– When OWREN = 0, then OVERW is frozen to 0 and CDATA field is protected against being overwritten
until being read.
– When OWREN = 1, then OVERW flags the CDATA field overwrite status.
0 Converted data has not been overwritten
1 Previous converted data has been overwritten before having been read
RESULT
This field reflects the mode of conversion for the corresponding channel.
00 Data is a result of Normal conversion mode.
01 Data is a result of Injected conversion mode.
10 Data is a result of CTU conversion mode.
11 Reserved.
CDATA Channel n converted data. Depending on the value of the MCR[WLSIDE] bit, the position of this bitfield
can be changed as shown in Figure 9-20
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-19