PXS20RM Datasheet, PDF (311/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
There is a register control block at the same level of the master port and slave port instantiations in the
XBAR. This control block ensures that all accesses are 32-bit supervisor accesses before passing them on
to the master ports.
The register outputs are connected directly to the state machine.
15.4.3.5 Master Port State Machine
15.4.3.5.1 Master Port State Machine States
The master side state machine’s main function is to monitor the activities of the master port. The state
machine has six states: busy, idle, waiting, stalled, steady state, first cycle error response and second
cycle error response.
The busy state is used when the master runs a BUSY cycle to the master port. The master port maintains
its request to the slave port if it currently owns the slave port; however, if it loses control of the slave port
it will no longer maintain its request. If the master port loses control of the slave port it will not be allowed
to make another request to the slave port until it runs a NSEQ or SEQ cycle.
The idle state is used when the master runs a valid IDLE cycle to the master port. The master port makes
no requests to the slave ports (disables the slave port decoder) and terminates the IDLE cycle.
The waiting state is used when the hsel signal is negated to the master port, indicating the master is
running valid cycles to a local slave other than the XBAR. In this case the max disables the slave port
decoder and holds hresp and hready negated.
The stalled state is used when the master makes a request to a slave port that is not immediately ready to
receive the request. In this case the state machine will direct the capture unit to send out the captured
address and control signals and will enable the slave port decoder to indicate a pending request to the
appropriate slave port.
The steady state state is used when the master port and slave port are in fully asynchronous mode, making
the XBAR completely transparent in the access. The state machine selects the appropriate slave’s hresp,
hready and hrdata to pass back to the master.
The first cycle error response and second cycle error response states are self explanatory. The XBAR
will respond with an error response to the master if the master tries to access an unimplemented memory
location through the XBAR (that is, a slave port that does not exist).
15.4.3.5.2 Master Port State Machine Slave Swapping
The design of the master side state machine is fairly straightforward. The one real decision to be made is
how to handle the master moving from one slave port access to another slave port access. The approach
that was taken is to minimize or eliminate when possible any “bubbles” that would be inserted into the
access due to switching slave ports.
The state machine will not allow the master to request access to another slave port until the current access
being made is terminated. This prevents a single master from owning two slave ports at the same time (the
slave port it is currently accessing and the slave port it wishes to access next).
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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