PXS20RM Datasheet, PDF (922/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
clock
interrupt request to processor
hardware vector enable
interrupt vector
0
interrupt acknowledge
read INTC_IACKR_PRCx
write INTC_EOIR_PRCx
INTVEC in INTC_IACKR_PRCx
0
PRI in INTC_CPR_PRCx
0
108
1
0
peripheral interrupt request 100
Figure 28-10. Software Vector Mode Handshaking Timing Diagram
28.5.3.2 Hardware Vector Mode Handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 28-11. As in
software vector mode, the INTC examines the peripheral and software settable interrupt requests, and
when it finds an asserted one with a higher priority than PRI in the associated INTC_CPR_PRC0, it asserts
the interrupt request to the associated processor. The INTVEC field in the associated
INTC_IACKR_PRC0 is updated with the preempting peripheral or software settable interrupt request’s
vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until
the next time the interrupt request to the associated processor is asserted. In addition, the value of the
interrupt vector to the associated processor matches the value of the INTVEC field in the associated
INTC_IACKR_PRC0. The rest of the handshaking is described in Section 28.2.1.2, Hardware Vector
Mode.
The handshaking near the end of the interrupt exception handler, that is the writing to the associated
INTC_EOIR_PRC0, is the same as in software vector mode. Refer to Section 28.5.3.1.2, End of Interrupt
Exception Handler.
28-16
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor