PXS20RM Datasheet, PDF (902/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Frequency-Modulated Phase-Locked Loop (FMPLL)
Table 27-6. MR Field Descriptions (continued)
Field
Description
16
SSCG_EN
17-31
INC_STEP
Frequency Modulation Enable
The SSCG_EN enables the frequency modulation.
0 = Frequency Modulation disabled
1= Frequency Modulation enabled
Increment step
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
incstep
=
ro
und


1---0-^{--02----1-}^{-5----5–----1}^-----M^-----O^--m---D^--d---P^----E^--M--R^---D-I^--O^--F---D^{---}
where:
md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md,
Downspread -- pk-pk=-2*md)
MDF: represents the nominal value of loop divider (NDIV in FMPLL Control Register)
27.6 Functional description
27.6.1 Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock
state, the FMPLL output clock (PHI) is derived by the reference clock (XOSC) through this relation:
phi=
-^x---^o---^s---^c----^---^l--^d---^f
idf  odf
where the value of idf, ldf and odf are set in CR and can be derived from Table 27-3, Table 27-4, and
Table 27-5.
See also Section 27.7, Requirements.
27.6.2 Progressive clock switching
Progressive clock switching is expected to be used on system clock. When changing the system clock to
run on a PLL frequency, the PLL locks at a divided frequency, then gradually decreases the division until
it is divided by 1. (See illustration below.) The effect is to gradually increase current consumption instead
of a single large increase.
PLL lock frequency
Division factor of
8, then 4, then 2, then 1
PLL output clock
Figure 27-4. Illustration of progressive clock switching
The gradual transition is further illustrated in Table 27-7.
27-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor