PXS20RM Datasheet, PDF (757/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
NOTE
The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and
TBIF are different from those mentioned in the Global Interrupt Flag and
Enable Register (FR_GIFER).
Table 26-36. FR_CIFR Field Descriptions
Field
Description
MIF
PRIF
CHIF
WUPIF
FAFBIF
FAFAIF
RBIF
TBIF
Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt
flag asserted.
0 No interrupt source has its interrupt flag asserted
1 At least one interrupt source has its interrupt flag asserted
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in
the Protocol Interrupt Flag Register 0 (FR_PIFR0) or Protocol Interrupt Flag Register 1 (FR_PIFR1)
is equal to 1.
0 All individual protocol interrupt flags are equal to 0
1 At least one of the individual protocol interrupt flags is equal to 1
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error
Flag Register (FR_CHIERFR) is equal to 1.
0 All CHI error flags are equal to 0
1 At least one CHI error flag is equal to 1
Wakeup Interrupt Flag — Provides the same value as FR_GIFER[WUPIF]
Receive FIFO Channel B Almost Full Interrupt Flag — Provides the same value as
FR_GIFER[FAFBIF]
Receive FIFO Channel A Almost Full Interrupt Flag — Provides the same value as
FR_GIFER[FAFAIF]
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive
message buffers (FR_MBCCSRn[MTD] = 0) the interrupt flag MBIF in the corresponding Message
Buffer Configuration, Control, Status Registers (FR_MBCCSRn) is equal to 1.
0 None of the individual receive message buffers has the MBIF flag asserted.
1 At least one individual receive message buffers has the MBIF flag asserted.
Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual single
or double transmit message buffers (FR_MBCCSRn[MTD] = 1) the interrupt flag MBIF in the
corresponding Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn) is equal
to 1.
0 None of the individual transmit message buffers has the MBIF flag asserted.
1 At least one individual transmit message buffers has the MBIF flag asserted.
26.5.2.32 System Memory Access Time-Out Register (FR_SYMATOR)
Base + 0x003E
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0
W
TIMEOUT
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Figure 26-32. System Memory Access Time-Out Register (FR_SYMATOR)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-45