PXS20RM Datasheet, PDF (562/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
5. Reads can now be done through the BIU in a Read Request type fashion. In the event of a BIU read
requested from an address that matches the address in the ADR register, expected data, and
corrections or detections should be observed based on data written into the UT0[DSI], UT1[DAI]
and/or UT2[DAI] registers. MCR[EER] and MCR[SBC] can be checked to evaluate the status of
reads done.
NOTE
In the event of an ECC error or Single Bit Correction, during the ECC logic
check (UTO[EIE] high), the ADR register will not be loaded, and the
address tagged to receive the UT0[DSI], UT1[DAI] and/or UT2[DAI]
values will be persevered.
6. Once completed, clear the UT0[EIE] bit to 0.
23.1.6 C90FL memory map and register definition
Table 23-1 shows how the array is memory mapped. Table 23-2 shows how the registers are mapped.
CAUTION
Software executing from flash memory must not write to registers that
control flash behavior (such as wait state settings or prefetch
enable/disable). Doing so can cause data corruption. On this chip, these
registers include PFCR0 and PFAPR.
NOTE
Flash memory configuration registers should be written only with 32-bit
write operations to avoid any issues associated with register incoherency
caused by bit fields spanning smaller size (8-, 16-bit) boundaries.
Table 23-1. C90FL flash memory map
FLASH_BASE address offset
Use
0x0
0x0000_4000
0x0001_0000
0x0001_C000
0x0002_0000
0x0003_0000
0x0004_0000
0x0006_0000
0x0008_0000
0x000C_0000
0x0010_0000 – 0x00EF_FFFF
Low Address Space
Mid Address Space
High Address Space
Reserved
Block
L0
L1
L2
L3
L4
L5
M0
M1
H0
H1
Size
(KB)
16
48
48
16
64
64
128
128
256
256
Partition
1
2
3
4
23-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor