PXS20RM Datasheet, PDF (1281/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

MBIST
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Table 42-19. MBIST partitioning (continued)
Type
Module
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
ROM
ROM
System RAM (128 KB plus ECC)
System RAM (128 KB plus ECC)
System RAM (128 KB plus ECC)
Platform I-Cache, SoR 0
Platform I-Cache, SoR 0
Platform I-Cache, SoR 0
Platform I-Cache, SoR 0
Platform Cache Tag, SoR 0
Platform Cache Tag, SoR 0
Platform Cache Tag, SoR 0
Platform Cache Tag, SoR 0
DMA memory, SoR 0
Platform I-Cache, SoR 1
Platform I-Cache, SoR 1
Platform I-Cache, SoR 1
Platform I-Cache, SoR 1
Platform Cache Tag, SoR 1
Platform Cache Tag, SoR 1
Platform Cache Tag, SoR 1
Platform Cache Tag, SoR 1
DMA memory, SoR 1
FlexCAN RX Buffer, rxim_ram
FlexCAN RX Buffer, rxim_ram
FlexCAN TX Buffer, mb_ram
FlexCAN TX Buffer, mb_ram
FlexRay LUT
FlexRay LUT
FlexRay Data Table
FlexRay ROM
BAM ROM
Self-Test Control Unit (STCU)
42.7 Self-test bypass and MBIST-only mode
The default STCU configuration as it is located in the test flash memory leads to a full self-test after an
STCU reset event (running all MBISTs and LBISTs).
Besides this, two configurations are available:
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
42-23