PXS20RM Datasheet, PDF (908/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
Software
Set/Clear
Interrupt
Registers
Peripheral
Interrupt
Requests
Flag Bits
8
n¹
Processor 0
Priority
LIFO
Pushed
Priority
4
Popped
Priority
4
Priority
Select
Registers
n¹ x
4-bits
Priority
Arbitrator
Highest
Priority
Interrupt
Requests
n¹
Request
Selector
4
Processor 0
Current
Priority
Register
Highest Priority
New
Priority
4
Current
Priority
4
Priority
Comparator
Lowest
Vector
Interrupt
Request
n¹
End of
Interrupt
Register
Vector
Encoder
Module
Configuration
Register
Vector Table
Entry Size ¹
Interrupt
Vector
9
Processor 0
Interrupt
Acknowledge
Register
Update Interrupt Vector
1
Hardware
Vector Enable
1
Interrupt
Vector
9
Interrupt
Request to
Processor
1
Interrupt Acknowledge
Push/Update/Acknowledge
Pop
Memory Mapped Registers
Non-Memory Mapped Logic
1 _{The total number of interrupt sources is 256.}
Figure 28-1. INTC block diagram
1
1
Slave
Interface
1 ^{for Reads}
& Writes
Peripheral
Bus
28.1.3 Features
• Supports 248 peripheral interrupt and 8 software-configurable interrupt request sources
• 9-bit vector
— Unique vector for each interrupt request source.
— Hardware connection to processor or read from register.
• Each interrupt source can be programmed to one of 16 priorities.
• Preemption
— Preemptive prioritized interrupt requests to processor.
— ISR at a higher priority preempts ISRs or tasks at lower priorities.
— Automatic pushing or popping of preempted priority to or from a LIFO.
— Ability to modify the ISR or task priority. Modifying the priority can be used to implement the
Priority Ceiling Protocol for accessing shared resources.
• Low latency - three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
28-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor