PXS20RM Datasheet, PDF (310/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
The first decoder is used to decode the mX_hsel_slv and control signals coming directly from the master,
telling the state machine where the master’s next access will be and if it is in fact a legal access. The second
decoder receives its input from the capture unit, so it may be looking directly at the signals coming from
the master or it may be looking at captured signals coming from the master, depending entirely on the state
of the targeted slave port. The second decoder is then used to generate the access requests that go to the
slave ports.
The capture unit is used to capture the address and control information coming from the master in the event
that the targeted slave port cannot immediately service the master. The capture unit is controlled by outputs
from the state machine which tell it to either pass through the original master signals or the captured
signals.
The register slice contains the registers associated with the specific master port. The registers have a
quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine.
The mux is used simply to select which slave’s read data is sent back to the master. The mux is controlled
by the state machine.
The state machine controls all aspects of the master port. It knows which slave port the master wants to
make a request to and controls when that request is made. It also has knowledge of each slave port,
knowing whether or not the slave port is ready to accept an access from the master port. This will
determine whether or not the master may immediately have its request taken by the slave port or whether
the master port will have to capture the master’s request and queue it at the slave port boundary.
15.4.3.2 Master Port Decoders
The decoders are very simple as they ensure an access request is allowed to be made and that the slave port
targeted is actually present in the design. The decoders feeding the state machine are always enabled. The
decoders that select the slave are enabled only when the master port controlling state machine wants to
make a request to a slave port. This is necessary so that if a master port is making an access to a slave port
and is being wait stated, and its next access is to a different slave port, the request to the second slave port
can be held off until the access to the first slave port is terminated.
The decoders also output a “hole decode” or illegal access signal which tells the state machine that the
master is trying to access a slave port that does not exist.
15.4.3.3 Master Port Capture Unit
The capture unit simply captures the state of the master’s address and control signals if the XBAR cannot
immediately pass the master’s request through to the proper slave port. The capture unit consists of a set
of flops and a mux which selects either the asynchronous path from address and control or the flopped
(captured) address and control information.
15.4.3.4 Master Port Registers
The registers in the master port are only those registers associated with this particular master port. The read
and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level
because not all the IP bus signals are routed this deep in the design.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor