PXS20RM Datasheet, PDF (888/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
5. FR_EEIAR[ADDR]:= I_ADDR;
- define the address for error injection; 0<= I_ADDR <= 0x0F
6. FR_EEIDR[DATA]:= D_DIST;
- define the data distortion pattern
7. FR_EEICR[CODE]:= C_DIST;
- define the checkbit distortion pattern
8. FR_EERICE[EIE]:=1;
- enable error injection
Application Write Access:
1. If (I_BANK==0) -> FR_MBCCFR(2*I_ADDR):= DATA;
If (I_BANK==1) -> FR_MBFIDR(2*I_ADDR):= DATA;
If (I_BANK==2) -> FR_MBIDXR(2*I_ADDR):= DATA;
If (I_BANK==3) -> FR_MBCCFR(2*I_ADDR+1):= DATA;
If (I_BANK==4) -> FR_MBFIDR(2*I_ADDR+1):= DATA;
If (I_BANK==5) -> FR_MBIDXR(2*I_ADDR+1):= DATA;
- write DATA to the defined injection bank and injection address
26.6.25.2 PE DRAM Error Injection
The following sequence describes an error injection sequence for the PE DRAM. This sequence includes
the setup of error injector followed by an application triggered write access to provoke an distortion of the
memory content. When the FlexRay module is in POC:default config, there are no limitations and impacts
of error injection for the application. For error injection out of POC:default config see Section 26.7.3, PE
DRAM Error Injection out of POC:default config.
Injector Setup:
1. FR_MCR[ECCE]:= 1;
- enable ecc functionality
2. FR_EERICE[EIE]:=I_MODE;
- configure error injection mode
3. FR_EEIAR[MID]:= 0;
- select PE DRAM for error injection
4. FR_EEIAR[BANK]:= I_BANK;
- define the bank for error injection; I_BANK = {0,1}
5. FR_EEIAR[ADDR]:= I_ADDR;
- define the address for error injection; 0<= I_ADDR <= 0x7F
6. FR_EEIDR[DATA]:= D_DIST;
- define the data distortion pattern
7. FR_EEICR[CODE]:= C_DIST;
- define the checkbit distortion pattern
8. FR_EERICE[EIE]:=1;
- enable error injection
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor