PXS20RM Datasheet, PDF (884/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
For each of the two memories exists two sets of internal registers to store the detection of one corrected
and one non-corrected memory error.
If a memory error is detected, the module checks whether the related error interrupt flag in the ECC Error
Interrupt Flag and Enable Register (FR_EEIFER) is set.
• If the error interrupt flag is set, the related internal error reporting register is not updated and the
related error overflow flag is set to 1 to indicate a loss of error condition.
• If the error interrupt flag is not set, the internal reporting register is updated and the error interrupt
flag is set to 1. If two or more memory errors of the same type are detected, the error for the bank
with the lower bank number will be reported, and the error overflow flag will be set to 1.
If a memory error is detected for at least two banks of one memory, the related error overflow flag is set
to 1 to indicate a loss of error condition.
26.6.24.2.1 PE DRAM Checkbits
The coding of the checkbits reported in ECC Error Report Code Register (FR_EERCR) for PE DRAM
memory errors is shown in Table 26-132. This table shows the implemented enhanced Hamming code. If
the error injection was applied to distort the checkbits, then the distorted checkbits are reported.
Table 26-131. PE DRAM checkbits coding
CODE
CODE
DATA
3
2
1
0
7
6
5
4
3
2
1
0
4¹
X
X
X
X
X
X
X
X
X
X
X
X
3²
-
-
-
-
X
X
X
X
-
-
-
-
2
-
-
-
-
X
-
-
-
X
X
X
-
1
-
-
-
-
-
X
X
-
X
X
-
X
0
-
-
-
-
-
X
-
X
X
-
X
X
NOTES:
1 _{The checkbit CODE[4] is set to 1 if and only if there is a even number of 1’s in columns with X.}
2 _{The checkbits CODE[3]... CODE[0] are set to 1 if and only if there is a odd number of 1’s in all columns with X.}
This coding of the checkbit ensures that neither 0x000 nor 0xFFF are valid code words and
written into the memory.
26.6.24.2.2 PE DRAM Syndrome
The coding of the syndrome reported in ECC Error Report Code Register (FR_EERCR) for PE DRAM
memory errors is shown in Table 26-132.
26-172
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor