PXS20RM Datasheet, PDF (770/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-54. FR_SSCCR Field Descriptions
Field
Description
SYF
NUF
SUF
STATUS
MASK[3:0]
Sync Frame Restriction — This bit is used to restrict the counter to received frames with the sync
frame indicator bit set to 1.
0 The counter is not restricted with respect to the sync frame indicator bit.
1 The counter is restricted to frames with the sync frame indicator bit set to 1.
Null Frame Restriction — This bit is used to restrict the counter to received frames with the null
frame indicator bit set to 0.
0 The counter is not restricted with respect to the null frame indicator bit.
1 The counter is restricted to frames with the null frame indicator bit set to 0.
Startup Frame Restriction — This bit is used to restrict the counter to received frames with the
startup frame indicator bit set to 1.
0 The counter is not restricted with respect to the startup frame indicator bit.
1 The counter is restricted to received frames with the startup frame indicator bit set to 1.
Slot Status Mask — This bit field is used to enable the counter with respect to the four slot status
error indicator bits.
STATUSMASK[3] – This bit enables the counting for slots with the syntax error indicator bit set to 1.
STATUSMASK[2] – This bit enables the counting for slots with the content error indicator bit set to 1.
STATUSMASK[1] – This bit enables the counting for slots with the boundary violation indicator bit set
to 1.
STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit
set to 1.
Table 26-55. Mapping between internal FR_SSCCRn and FR_SSCRn
Condition Register
FR_SSCCR0
FR_SSCCR1
FR_SSCCR2
FR_SSCCR3
Condition Defined for Register
FR_SSCR0
FR_SSCR1
FR_SSCR2
FR_SSCR3
26.5.2.48 Slot Status Registers (FR_SSR0–FR_SSR7)
Base + 0x0068 (FR_SSR0)
Base + 0x006A (FR_SSR1)
Base + 0x006C (FR_SSR2)
Base + 0x006E (FR_SSR3)
Base + 0x0070 (FR_SSR4)
Base + 0x0072 (FR_SSR5)
Base + 0x0074 (FR_SSR6)
Base + 0x0076 (FR_SSR7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R VFB SYB NFB SUB SEB CEB BVB TCB VFA SYA NFA SUA SEA CEA BVA TCA
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-48. Slot Status Registers (FR_SSR0–FR_SSR7)
26-58
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor