PXS20RM Datasheet, PDF (126/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Operating Modes
The Redundancy Control Checker Units (RCCU) at the outputs of the SoR to the periphery bus, to the
Flash subsystem and to the SRAM subsystem detect such propagating failures due to data on the external
busses being inconsistent between both processing units. Thus the RCCUs implement the modified fault
isolation in that they detect but not prevent the propagation of a non-common cause failure at the point
where the two redundant channels are merged into a single actuator or recipient. Isolation of the overall
system is then achieved by the Fault Collection and Control Unit (FCCU) signaling an error, thereby
allowing the device or application to react appropriately.
4.3 Decoupled Parallel Mode (DPM)
In this operating mode, each CPU core and connected channel runs independently from the other core, and
the redundancy checkers (RCCU) are disabled.
At a given frequency, operating the chip in DPM offers a performance increase of approximately 1.6 over
operating the chip in LSM.
In this operating mode, the chip boots with Core_0 enabled and Core_1 disabled directly after most resets.
After a short external or short 'functional' reset, core1 is immediately enabled if it was enabled prior to the
reset. Software running on Core_0 can enable Core_1 at any time, and once core1 has been enabled, it
cannot be disabled by software. While Core_1 is disabled, it is not clocked, thus minimizing the chip's
overall current consumption during this time.
See the tables in Chapter 2, Memory Map, for information on how memory is configured and accessed in
DPM.
4.4 Selecting LSM or DPM
The operating mode (LSM or DPM) on PXS20 is determined by the LSM_DPM user option bit in the
shadow block of the flash memory. This user option bit is described in Section 23.1.7, User option bits,
and is physically accessed using the UOPS[UOPT] field in the SSCM (see Section 48.3.1.8, User Option
Status Register (UOPS)).
4.4.1 Entering LSM
By default, PXS20 is configured to start in LSM (LSM_DPM = 1).
4.4.2 Entering DPM
4.4.2.1 Dual-core boot concepts
Entering DPM implies a dual-core boot. The key concept to a dual-core boot is that it is nothing more than
a typical single-core boot, except that it starts another single-core boot. The initialization of interrupts,
stack, and other parameters needs to be performed on each core. In other words, it is a single-core boot
performed twice.
Figure 4-1 shows a simplification of this boot process.
PXS20 Microcontroller Reference Manual, Rev. 1
4-2
Freescale Semiconductor