PXS20RM Datasheet, PDF (217/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
• contains a set of registers to control clock dividers for divided clock generation
• supports multiple clock sources and maps their address spaces to its memory map
• generates an output clock
• guarantees glitch-less clock transitions when changing the system clock selection
• supports 8, 16 and 32-bit wide read/write accesses
11.2 External signal description
The MC_CGM delivers an output clock to the port pin B[6] for off-chip use and/or observation.
11.3 Memory map and register definition
Table 11-1. MC_CGM register description
Address
Name
Description
Size
0xC3FE_0370 CGM_OC_EN Output Clock Enable
word
0xC3FE_0374 CGM_OCDS_S Output Clock Division Select
byte
C
0xC3FE_0378 CGM_SC_SS System Clock Select Status
byte
0xC3FE_037 CGM_SC_DC0 System Clock Divider
byte
C
Configuration 0
0xC3FE_0380 CGM_AC0_SC Aux Clock 0 Select Control
word
0xC3FE_0384 CGM_AC0_DC0 Aux Clock 0 Divider Configuration 0 byte
0xC3FE_0385 CGM_AC0_DC1 Aux Clock 0 Divider Configuration 1 byte
0xC3FE_0388 CGM_AC1_SC Aux Clock 1 Select Control
word
0xC3FE_038 CGM_AC1_DC0 Aux Clock 1 Divider Configuration 0 byte
C
0xC3FE_0390 CGM_AC2_SC Aux Clock 2 Select Control
word
0xC3FE_0394 CGM_AC2_DC0 Aux Clock 2 Divider Configuration 0 byte
0xC3FE_0398 CGM_AC3_SC Aux Clock 3 Select Control
word
0xC3FE_03A CGM_AC4_SC Aux Clock 4 Select Control
0
word
User
read
read
read
read
read
read
read
read
read
read
read
read
read
Access
Superviso
r
Test
read/write read/write
read/write read/write
read
read
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
read/write read/write
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
• not change register content
• cause a transfer error
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
11-3