PXS20RM Datasheet, PDF (972/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
As shown in Figure 30-10, the output of the protection violation logic is the error signal, that is, error
= protection_violation.
The access evaluation macro then uses the hit_b and error signals to form two outputs. The combined
(hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error)
is used as the input to MPU_EDRn (error detail register) in the event of an error.
The critical timing arc through the access evaluation macro involves the delay from the arrival of
haddr[*] through the two magnitude comparators and through the hit_b generation as shown in
Figure 30-11.
AHB_ap
start
RGDn
end
hit_b
>>
error
Figure 30-11. Access evaluation macro critical timing path
30.7.2 Putting it all together and AHB error terminations
For each AHB slave port being monitored, the MPU performs a reduction-AND of all the individual
(hit_b | error) terms from each access evaluation macro. This expression then terminates the bus
cycle with an error and reports a protection error for three conditions:
1. If the access does not hit in any region descriptor, a protection error is reported.
2. If the access hits in a single region descriptor and that region signals a protection violation, then a
protection error is reported.
3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then
a protection error is reported.
The third condition reflects that priority is given to permission granting over access denying for
overlapping regions as this approach provides more flexibility to system software in region descriptor
assignments. For an example of the use of overlapping region descriptors, see Section 30.9, Application
information.
The handling of the AHB bus cycle with a protection error requires two distinct actions. First, recall the
protection error logic resides within the AHB address phase pipeline stage. In the event of a protection
error, the reference must be inhibited from entering the AHB data phase for the targeted slave device.
Stated differently, the reference’s address phase must be aborted as viewed by the targeted slave device.
30-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor