PXS20RM Datasheet, PDF (955/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 30
Memory Protection Unit (MPU)
Memory Protection Unit (MPU)
30.1 Introduction
The Memory Protection Unit (MPU) provides hardware access control for all memory references
generated in a device. Using region descriptors which define memory spaces and their associated access
rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of
each transfer. Memory references that have sufficient access control rights are allowed to complete, while
references that are not mapped to any region descriptor or have insufficient rights are terminated with a
protection error response.
The MPU implements a set of program-visible region descriptors which are used to monitor all system bus
addresses. The result is a hardware structure with a two-dimensional connection matrix, where the region
descriptors represent one dimension and the individual system bus addresses and attributes are the second
dimension.
30.2 Block diagram
A simplified block diagram of the MPU module is shown in Figure 30-1. The hardware’s two-dimensional
connection matrix is clearly visible with the basic access evaluation “macro” shown as the replicated
submodule block. The AHB¹ bus slave ports (s{0,1,2,3}_h*) are shown on the left side of the diagram, the
region descriptor registers in the middle and the IPS bus interface (ips_*) on the right side. The evaluation
macro contains the two magnitude comparators connected to the start and end address registers from each
region descriptor (rgdn) as well as the combinational logic blocks to determine the region hit and the
access protection error. For information on the details of the access evaluation macro, see Section 30.7.1,
Access evaluation macro.
1.ARM’s Advanced High-performance Bus
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
30-1