PXS20RM Datasheet, PDF (803/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Field
DUP
DVAL
EDS
LCKS
MBIF
FlexRay Communication Controller
Table 26-89. FR_MBCCSRn Field Descriptions (continued)
Description
Message Buffer Status
Data Updated — This status bit indicates whether the frame header in the message buffer header
field and the data in the message buffer data field were updated after a frame reception.
0 Frame Header and Message buffer data field not updated
1 Frame Header and Message buffer data field updated
Data Valid — For receive message buffers this status bit indicates whether the message buffer
data field contains valid frame data. For transmit message buffers the status bit indicates if a
message is transferred again due to the state transmission mode of the message buffer.
0 receive message buffer contains no valid frame data / message is transmitted for the first time
1 receive message buffer contains valid frame data / message will be transferred again
Enable/Disable Status — This status bit indicates whether the message buffer is enabled or
disabled.
0 Message buffer is disabled.
1 Message buffer is enabled.
Lock Status — This status bit indicates the current lock status of the message buffer.
0 Message buffer is not locked by the application.
1 Message buffer is locked by the application.
Message Buffer Interrupt Flag — This flag is set when the slot status field of the message buffer
was updated after frame transmission or reception, or when a transmit message buffer was just
enabled by the application.
0 No such event
1 Slot status field updated or transmit message buffer just enabled
26.5.2.79 Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn)
Base + 0x0102 (FR_MBCCFR0)
Base + 0x010A (FR_MBCCFR1)
...
Base + 0x02FA (FR_MBCCFR63)
16-bit write access required
Write: POC:config or MB_DIS
0
1
2
3
4
R
MTM CHA CHB CCFE
W
5
6
7
8
CCFMSK
9
10
11
12
13
14
15
CCFVAL
Reset -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Figure 26-110. Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn)
This register contains message buffer configuration data for the transmission mode, the channel
assignment, and for the cycle counter filtering. For detailed information on cycle counter filtering, refer to
Section 26.6.7.1, Message Buffer Cycle Counter Filtering.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-91