PXS20RM Datasheet, PDF (1246/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Reset Generation Module (MC_RGM)
Table 41-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions (continued)
Field
Description
D_CORE
D_JTAG
Disable core reset
0 A core reset event triggers a reset sequence
Disable JTAG initiated reset
0 A JTAG initiated reset event triggers a reset sequence
41.3.1.4 Destructive Event Reset Disable Register (RGM_DERD)
Address 0xC3FE_4006
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
000000000
00
W
Reset^* 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
* _{This register is reset if and only if one of thefollowing occurs:}
• Power up
• 1.2 V low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain
their value)
Figure 41-6. Destructive Event Reset Disable Register (RGM_DERD) for cut1
Address 0xC3FE_4006
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0000000
00
W
Reset^* 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
* _{This register is reset if and only if one of thefollowing occurs:}
• Power up
• 1.2 V low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain
their value)
Figure 41-7. Destructive Event Reset Disable Register (RGM_DERD) for cut2/3
This register provides dedicated bits to disable particular destructive reset sources. It can be accessed in
read-only in supervisor mode, test mode, and user mode.
41-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor