PXS20RM Datasheet, PDF (865/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
While the protocol is in POC:config state, the application must program the offsets for the tables into the
Sync Frame Table Offset Register (FR_SFTOR).
26.6.12.4 Sync Frame ID and Sync Frame Deviation Table Generation
The application controls the generation process of the Sync Frame ID and Sync Frame Deviation Tables
into the FlexRay memory area using the Sync Frame Table Configuration, Control, Status Register
(FR_SFTCCSR). A summary of the copy modes is given in Table 26-124.
Table 26-124. Sync Frame Table Generation Modes
OPT
FR_SFTCCSR
SDVEN
SIDEN
Description
0
0
0
No Sync Frame Table copy
0
0
1
Sync Frame ID Tables will
be copied continuously
0
1
0
Reserved
0
1
1
Sync Frame ID Tables and
Sync Frame Deviation
Tables will be copied
continuously
1
0
0
No Sync Frame Table copy
1
0
1
Sync Frame ID Tables for
next even-odd-cycle pair
will be copied
1
1
0
Reserved
1
1
1
Sync Frame ID Tables and
Sync Frame Deviation
Tables for next
even-odd-cycle pair will be
copied
The Sync Frame Table generation process is described in the following for the even cycle. The same
sequence applies to the odd cycle.
If the application has enabled the sync frame table generation by setting FR_SFTCCSR[SIDEN] to 1, the
CC starts the update of the even cycle related tables after the start of the NIT of the next even cycle. The
CC checks if the application has locked the tables by reading the FR_SFTCCSR[ELKS] lock status bit. If
this bit is set, the CC will not update the table in this cycle. If this bit is cleared, the CC locks this table and
starts the table update. To indicate that these tables are currently updated and may contain inconsistent
data, the CC clears the even table valid status bit FR_SFTCCSR[EVAL]. Once all table entries related to
the even cycle have been transferred into the FlexRay memory area, the CC sets the even table valid bit
FR_SFTCCSR[EVAL] and the Even Cycle Table Written Interrupt Flag EVT_IF in the Protocol Interrupt
Flag Register 1 (FR_PIFR1). If the interrupt enable flag EVT_IE is set, an interrupt request is generated.
To read the generated tables, the application must lock the tables to prevent the CC from updating these
tables. The locking is initiated by writing a 1 to the even table lock trigger FR_SFTCCSR[ELKT]. When
the even table is not currently updated by the CC, the lock is granted and the even table lock status bit
FR_SFTCCSR[ELKS] is set. This indicates that the application has successfully locked the even sync
tables and the corresponding status information fields SFRA, SFRB in the Sync Frame Counter Register
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-153