PXS20RM Datasheet, PDF (255/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Cross-Triggering Unit (CTU)
13.5.1 ADC commands list
The ADC can be controlled by the CPU (CPU Control Mode) and by the CTU (CTU Control Mode). The
CTU can control the ADC from sending an ADC command only when the ADC is in CTU control mode.
During the CTU control mode, the CPU is able to write to the ADC registers but it can not start a new
conversion. A control bit is allowed to select from the classic interface of the CTU control mode. Once
selected, no change is possible unless a reset occurs.
The SU uses a Commands List in order to select the command to send to the ADC when a trigger event
occurs. The commands list can hold 24 16-bits commands (see Section 13.5.2, ADC commands list
format) and it is double-buffered, i.e. the commands list can be updated at any time between two
consecutive MRS, but the changes become workable only after the next MRS occurs, and a correct reload
is performed. In order to manage the commands list, 5 bits are available in the CLCRx (ADC Commands
List Control Register x), for the position of the first command in the list of commands for each trigger
event. The number of commands piloted by the same trigger event is defined directly in the commands list.
For each command there is a bit which defines whether it is the first command of a commands list, or not.
13.5.2 ADC commands list format
The two ADCs support the Single Conversion Mode (1 bit in the ADC command format allows selection
of the conversion mode), and the Dual Conversion Mode (the sampling phases and the conversion phases,
are performed at the same time, the storage of the results are performed in series). The result of each
conversion, in both modes, can be stored in one of the 4 available FIFOs. In dual conversion mode, both
ADCs must store the result of their conversion in the same FIFO. If the access to the FIFO is in the same
clock cycle, the ADC unit A has the priority, otherwise the first ADC which ends its conversion, will write
as first in the FIFO. 4 analog channels are shared across the 2 ADCs and the total number of channels is
28 (12 + 12 + 4 shared channels), i.e. 16 channels for each ADC (12 + 4 shared channels). The dual
conversion mode on the same physical channel is not allowed, but the dual conversion mode on the same
channel number is allowed. According to this, if, in dual conversion mode, the channel number is the same
for both the ADCs and the selected channel is one of the shared channels, the CTU will detect an invalid
command. In dual conversion mode 4 bits for each ADC are used to select the channel number and the
conversion mode selection bit is used to select the dual conversion mode. If the single conversion mode is
selected, 5 bits of the 8 bits reserved to select the channels in dual conversion mode are re-used to select
the channel (4 bits) and the ADC unit (1 bit). See Section 13.10.9, Commands list register x (x = 1,...,24)
(CLRx).
The interrupt request bit is used as an interrupt request to the CPU when ADC will complete the command
with this bit set and it is only for CTU internal use. Before the next command to the CTU controls is sent,
the value of the first command bit, is checked to see if it is the current command is the first command of a
new stream of consecutive commands or not. If not, the CTU sends the command. According to the
previous considerations, the commands in the list will allow to have control on:
• Channel A: number of ADC channel to sample from ADC unit A (4 bits);
• Channel B: number of ADC channel to sample from ADC unit B (4 bits);
• FIFO selection bits for the ADC unit A/B (2 bits);
• Conversion Mode selection bit: 0 Single Conversion Mode - 1 Dual Conversion Mode;
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
13-9