PXS20RM Datasheet, PDF (1007/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

31.10.4 LIN error status register (LINESR)
LIN Controller (LINFlexD)
Offset: 0x0C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SZF OCF BEF CEF
FEF BOF 0 0 0 0 0 0 NF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-21. LIN error status register (LINESR)
Table 31-16. LINESR field descriptions
Field
SZF
OCF
BEF
CEF
SFEF
BDEF
IDPEF
Description
Stuck at zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by
software.
Output Compare Flag
0: No output compare event occurred
1: The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this bit
is set and IOT bit in LINTCSR is set, LINFlexD moves to Idle state.
If LTOM bit in LINTCSR register is set then OCF is reset by hardware in Initialization mode. If LTOM bit
is reset, then OCF maintains its status whatever the mode is.
Bit Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a bit error. This
error can occur during response field transmission (Slave and Master modes) or during header
transmission (in Master mode).
This bit is cleared by software.
Checksum error Flag
This bit is set by hardware and indicates that the received checksum does not match the hardware
calculated checksum.
This bit is cleared by software.
Note: This bit is never set if CCD or CFD bit in LINCR1 register is set.
Synch Field Error Flag
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field).
Break Delimiter Error Flag
This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one
bit time).
Identifier Parity Error Flag
This bit is set by hardware and indicates that a Identifier Parity error occurred.
Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER is
set.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-31