PXS20RM Datasheet, PDF (883/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.6.24 Memory Content Error Detection
The FlexRay module provides integrated memory content error detection for both the CHI LRAM and PE
DRAM, and memory content error correction for the PE DRAM. The memory error detection for the CHI
LRAM uses an standard Hamming code with a Hamming distance of 3 and detects all single-bit and
double-bit errors (SEDDED). The memory error detection and correction for the PE DRAM uses an
enhanced Hamming code with a Hamming distance of 4 and detects and corrects all single-bit errors and
detects all double-bit errors (SECDED).
This section describes the reporting of the occurrence of memory content errors, the reaction of the module
on the occurrence, and how the application can inject memory errors in order to trigger the report and
response behavior.
26.6.24.1 Memory Error Types
A memory error is the distortion of one or more bits read out of the memory. The reading of the values of
all zeros and all ones is considered as an special case. The FlexRay module detects and indicates the
memory errors as shown in Table 26-130. The entries on the top have higher priority.
Each memory read access reads out all banks of the addressed row, and runs error detection on all banks,
even in the case that the application has triggered a read from only one bank. This may lead to the reporting
of an memory error if at least one bank contains a memory error, even if an error free bank has been read.
Table 26-130. Detected Memory Error Types
Memory
CHI LRAM
PE DRAM
CHI LRAM
PE DRAM
CHI LRAM
PE DRAM
CHI LRAM
PE DRAM
CHI LRAM
Priority
0 (highest)
1 (lowest)
PE DRAM
Memory Data
All Zero’s
Indication
No Error - Valid Data
Non-Corrected Error
All One’s
One Bit Flipped
Non-Corrected Error
Non-Corrected Error
Corrected Error
Two Bits Flipped
Three or more
Bits Flipped
Non-Corrected Error
one out of {No error, Non-Corrected Error}, defined by
coding given in Section 26.6.24.2.3, CHI LRAM
Checkbits, and Section 26.6.24.2.3, CHI LRAM
Checkbits.
one out of {No error, Corrected Error, Non-Corrected
Error}, defined by coding given in Section 26.6.24.2.1, PE
DRAM Checkbits, and Section 26.6.24.2.2, PE DRAM
Syndrome.
26.6.24.2 Memory Error Reporting
The memory error reporting is enabled only if the ECC functionality enable bit ECCE in the Module
Configuration Register (FR_MCR) is set.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-171