PXS20RM Datasheet, PDF (409/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
19.2.1.7 eDMA Set Enable Error Interrupt (DMASEEI)
The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the DMAEEIL
register to enable the error interrupt for a given channel. The data value on a register write causes the
corresponding bit in the DMAEEIL register to be set. A data value of 64 to 127 (regardless of the number
of implemented channels) provides a global set function, forcing the entire contents of DMAEEIL to be
asserted. If the NOP bit is set, the command is ignored. This allows multiple byte registers to be written as
a 32-bit word. Reads of this register return all zeroes.
See Figure 19-8 and Table 19-10 for the DMASEEI definition.
Register address: DMA_Offset + 0x001A
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
SEEI
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-8. eDMA Set Enable Error Interrupt (DMASEEI) Register
Name
NOP
SEEI
Table 19-10. DMASEEI field descriptions
Description
Value
No Operation
Set Enable Error Interrupt
0 Normal operation
1 No operation, ignore the other bits in the register
See the field structure in Table 19-11
Bit number
0
1–2
3–6
Table 19-11. DMASEEI[SEEI] field structure
Description
“Set all” bit:
0 Affects only the channel specified in bit numbers 4–7
1 Affects all channels (bit numbers 4–7 are ignored)
Reserved
Set the corresponding bit in DMAEEIL
19.2.1.8 eDMA Clear Enable Error Interrupt (DMACEEI)
The DMACEEI register provides a simple memory-mapped mechanism to clear a given bit in the
DMAEEIL register to disable the error interrupt for a given channel. The data value on a register write
causes the corresponding bit in the DMAEEIL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAEEIL to be zeroed, disabling all eDMA request inputs. If the NOP is set, the command is ignored.
This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes.
See Figure 19-9 and Table 19-12 for the DMACEEI definition.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
19-13