PXS20RM Datasheet, PDF (675/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
The fault decoder disables PWM pins selected by the fault logic and the disable mapping register
(DISMAP). See Figure 25-27 for an example of the fault disable logic. Each bank of bits in DISMAP
control the mapping for a single PWM pin. Refer to Table 25-2.
The fault protection is enabled even when the PWM module is not enabled; therefore, a fault will be
latched in and must be cleared in order to prevent an interrupt when the PWM is enabled.
DISA3 DISA2 DISA1 DISA0
FAULT0
FAULT1
FAULT2
FAULT3
Wait Mode
WAITEN
Debug Mode
DBGEN
Stop Mode
DISABLE
PWMA
Figure 25-27. Fault Decoder for PWMA
PWM Pin
PWMA
PWMB
PWMX
Table 25-2. Fault Mapping
Controlling Register Bits
DISA[3:0]
DISB[3:0]
DISX[3:0]
25.3.3.11.1 Fault Pin Filter
Each fault pin has a programmable filter that can be bypassed. The sampling period of the filter can be
adjusted with the FILT_PER field of the FFILTx register. The number of consecutive samples that must
agree before an input transition is recognized can be adjusted using the FILT_CNT field of the same
register. Setting FILT_PER to all 0 disables the input filter for a given FAULTx pin.
Upon detecting a logic 0 on the filtered FAULTx pin (or a logic 1 if FLVLx is set), the corresponding
FFPINx and fault flag, FFLAGx, bits are set. The FFPINx bit remains set as long as the filtered FAULTx
pin is zero. Clear FFLAGx by writing a logic 1 to FFLAGx.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-29