PXS20RM Datasheet, PDF (242/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Monitor Unit (CMU)
12.3.6 Measurement duration register (CMU_MDR)
Address: Base + 0x18
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0
W
MD[19:16]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MD[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-6. Measurement duration register (CMU_MDR)
Table 12-9. CMU_MDR field descriptions
Field
MD
Description
Measurement duration bits
This register displays the measured duration in terms of IRCOSC clock cycles. This value is loaded in
the frequency meter down-counter. When CMU_CSR[SFM] = 1, the down-counter starts counting.
12.4 Functional description
The names of the clocks involved in this block have the following meaning:
• XOSC_CLK: clock coming from the XOSC
• IRCOSC_CLK: clock coming from the IRCOSC
• CK_PLL: clock coming from the FMPLL
• F_{XOSC_CLK}: frequency of external crystal oscillator clock
• F_{IRCOSC_CLK}: frequency of low frequency internal RC oscillator
• FPLL: frequency of FMPLL clock
12.4.1 XOSC clock monitor
The XOSC clock is monitored by CMU_0. If F_{XOSC_CLK} is smaller than F_{IRCOSC_CLK} divided by
2^{CMU_CSR[RCDIV]} and the XOSC is ‘ON’ and stable as signaled by the MC_ME, then:
• CMU_ISR[OLRI] is set.
• A failure event OLR is signaled to the MC_RGM and FCCU, which in turn can generate a
‘functional' reset, a SAFE mode request, or an interrupt.
NOTE
The XOSC monitor may produce a false event when F_{XOSC_CLK} is less than
2F_{IRCOSC_CLK}2^{CMU_CSR[RCDIV]} due to an accuracy limitation of the
compare circuitry.
12-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor