PXS20RM Datasheet, PDF (925/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
bl
ISRx
# branch to ISR for interrupt with vector x
epilog:
lis
ori
li
stw
r3,hi(INTC_EOIR_PRC0)
r3,r3,lo(INTC_EOIR_PRC0)
r4,0x0
r4,0x0(r3)
# form INTC_EOIR_PRC0 address
# form 0 to write to INTC_EOIR_PRC0
# store to INTC_EOIR_PRC0, informing INTC to lower priority
code to restore context required by EABI and disable processor recognition of interrupts
code to restore SRR0 and SRR1
rfi
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr
# branch to epilog
28.6.3 Code Compression’s Impact on Vector Table
The entries in the vector table in the interrupt exception handler example in Section 28.6.2.1, Software
vector mode, are addresses of ISRs. A vector table also can be written whose entries are branches to ISRs.
The instruction flow branches to the entry in the vector table corresponding to the vector of the peripheral
or software settable interrupt request, and then the instruction flow branches to the corresponding ISR.
While a vector table of addresses of ISRs is not affected by code compression, a vector table of branches
to ISRs can be affected. Code compression techniques can produce for some cases instructions that are
wider than 32 bits but less than 64 bits. If the vector table is compressed and some instructions are wider
than 32 bits, the VTES_PRC0 bit in Section 28.4.3, INTC Block Configuration Register (INTC_BCR),
can be set. Each entry in the vector table then can occupy 64 bits.
28.6.4 ISR, RTOS, and Task Hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in Section 28.4.4, INTC Current
Priority Register for Processor 0 (INTC_CPR_PRC0), having a value of 0. The RTOS will execute the
tasks according to whatever priority scheme that it may have, but that priority scheme is independent and
has a lower priority of execution than the priority scheme of the INTC. In other words, the ISRs execute
above INTC_CPR_PRC0 priority 0 and outside the control of the RTOS, the RTOS executes at
INTC_CPR_PRC0 priority 0, and while the tasks execute at different priorities under the control of the
RTOS, they also execute at INTC_CPR_PRC0 priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR_PRC0 while the shared resource is being accessed.
An ISR whose PRIx in Section 28.4.8, INTC Priority Select Registers (INTC_PSR0_3 -
INTC_PSR252_255), has a value of 0 will not cause an interrupt request to the selected processor, even if
its peripheral or software settable interrupt request is asserted. For a peripheral interrupt request, not
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
28-19