PXS20RM Datasheet, PDF (1157/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Periodic Interrupt Timer (PIT)
Timer interrupts can be disabled by setting the TIE bits to zero. The timer interrupt flags (TIF) are set to 1
when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that TIF bit.
36.5 Initialization and Application Information
36.5.1 Example Configuration
In the example configuration:
• the PIT clock has a frequency of 50 MHz
• timer 1 shall create an interrupt every 5.12 ms
• timer 3 shall create a trigger event every 30 ms
First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITCTRL register.
The 50 MHz clock frequency equates to a clock period of 20 ns . Timer 1 needs to trigger every 5.12 ms/20
ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. The value for the LDVAL register
trigger would be calculated as (period / clock period) -1.
This means that LDVAL1 with 0003E7FF hex and LDVAL3 with 0016E35F hex.
The interrupt for Timer 1 is enabled by setting TIE in the TCTRL1 register. The timer is started by writing
a 1 to bit TEN in the TCTRL1 register.
Timer 3 shall be used only for triggering. Therefore Timer 3 is started by writing a 1 to bit TEN in the
TCTRL3 register, bit TIE stays at 0.
The following example code matches the described setup:
// turn on PIT
PIT_CTRL = 0x00;
// Timer 1
PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cycles
PIT_TCTRL1 = TIE; // enable Timer 1 interrupts
PIT_TCTRL1 |= TEN; // start timer 1
// Timer 3
PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles
PIT_TCTRL3 = TEN; // start timer 3
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
36-9