PXS20RM Datasheet, PDF (303/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
Name
MSTR_0
Table 15-7. Master Priority Register descriptions (continued)
Description
Settings
Master 0 Priority - These bits set the arbitration priority 000This master has the highest priority
for master port 0 on the associated slave port.
when accessing the slave port.
These bits are initialized by hardware reset.
The reset value is 000
111This master has the lowest priority
when accessing the slave port.
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO
(Read Only) bit has been set in the slave General Purpose Control Register the Master Priority Register
can only be read from, attempts to write to it will have no effect on the MPR and result in an error response.
NOTE
No two available master ports may be programmed with the same priority
level. Attempts to program two or more available masters with the same
priority level will result in an error response and the MPR will not be
updated.
15.3.2.2 Slave General Purpose Control Register
The Slave General Purpose Control Register (SGPCR) controls several features of each slave port.
The Read Only (RO) bit will prevent any registers associated with this slave port from being written to
once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only
a reset condition will allow it to be written again.
The Halt Low Priority (HLP) bit will set the priority of the max_halt_request input to the lowest possible
priority for initial arbitration of the slave ports. By default it is the highest priority. Setting this bit will not
effect the max_halt_request from attaining highest priority once it has control of the slave ports.
The PCTL bits determine how the slave port will park when no master is actively making a request. The
available options are to park on the master defined by the PARK bits, park on the last master to use the
slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive
states when no master is requesting an access. The low power park feature can result in an overall power
savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any
master tries to access it when it is not in use because it will not be parked on any master.
The PARK bits determine which master the slave will park on when no master is making an active request
and the max_halt_request input is negated. Please use caution to only select master ports that are actually
present in the design. If the user programs the PARK bits to a master not present in the current design
implementation undefined behavior will result.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
15-9