PXS20RM Datasheet, PDF (1104/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
• Self-transition requests (e.g. RUN0  RUN0) are not considered as invalid even when the mode
transition process is active (i.e. S_MTRANS is ‘1’). During the low-power mode exit process, if
the system is not able to enter the respective RUN0…3 mode properly (i.e. all status bits of the
register match with configuration bits in the ME_<mode>_MC register), then software can only
request the SAFE or RESET mode. It is not possible to request any other mode or to go back to the
low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register
is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’.
32.4.5.3 SAFE Mode Transition Interrupt
Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due
to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is
generated if the mask bit M_SAFE of ME_IM register is ‘1’.
The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by
the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system
is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending
bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered by
a software request (i.e. programming of register).
32.4.5.4 Mode Transition Complete interrupt
Whenever the system fully completes a mode transition (i.e. the S_MTRANS bit of register transits from
‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and an interrupt request is
generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not set when
entering low-power modes HALT0 and STOP0 in order to avoid the same event requesting the immediate
exit of these low-power modes.
32.4.6 Peripheral Clock Gating
During all device modes, each peripheral can be associated with a particular clock gating policy
determined by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running
modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software according
to the needs of the application. Each configuration register contains a mode bit which determines whether
or not a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the
RUN_CFG bit field of the ME_PCTL0…143 registers.
The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power
modes HALT0 and STOP0. All configurations are programmable by software according to the needs of
the application. Each configuration register contains a mode bit which determines whether or not a
peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the
LP_CFG bit field of the ME_PCTL0…143 registers.
32-48
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor