PXS20RM Datasheet, PDF (910/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
28.2.2 Debug Mode
The INTC operation in debug mode is identical to its operation in normal mode.
28.2.3 Stop Mode
The INTC supports the stop mode mechanism. The INTC can have its clock input disabled at any time by
the clock driver on the SoC. While its clocks are disabled, the INTC registers are not accessible.
Some SoC applications require that any peripheral interrupt request source be able to awaken a portion or
all of the SoC from stop mode. Since the INTC requires clocking in order for a peripheral interrupt request
to generate an interrupt request to the processor, it does not support that requirement if it is not clocked.
28.2.4 Factory Test Mode
All INTC registers are accessible in factory test mode.
28.3 External Signal Description
The INTC has no external MCU signals.
28.4 Memory map/register definition
28.4.1 Memory map
Table 28-1 is the INTC memory map.
Table 28-1. INTC memory map
Offset from
INTC_BASE
Register
Access¹ Reset value²
Location
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
INTC Block Configuration Register (INTC_BCR)
Reserved
INTC Current Priority Register for Processor 0
(INTC_CPR_PRC0)
Reserved
INTC Interrupt Acknowledge Register for Processor
0 (INTC_IACKR_PRC0)
Reserved
INTC End Of Interrupt Register for Processor 0
(INTC_EOIR_PRC0)
Reserved
INTC Software Set/Clear Interrupt Register 0 - 3
(INTC_SSCIR0_3)
R/W
R/W
R/W
R
R/W
0x0000_0000 on page 28-6
0x0000_000F on page 28-7
0x0000_0000 on page 28-8
0x0000_0000 on page 28-9
0x0000_0000 on page 28-9
28-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor