PXS20RM Datasheet, PDF (474/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
Table 20-16. Interrupt summary
Core Interrupt Interrupt
interrupt flag
enable
Name
Description
TC0IR–
TC5IR¹
TCF
TCF1
TCFIE
TCF1IE
Compare interrupt
Compare 1 interrupt
Compare of counter and related compare register
Compare of the counter and COMP1 register
TCF2 TCF2IE Compare 2 interrupt Compare of the counter and COMP2 register
TOF
TOFIE
Overflow interrupt Generated on counter roll-over or roll-under
IELF
IELFIE Input Low Edge interrupt Falling edge of the secondary input signal
IEHF
IEHFIE Input High Edge interrupt Rising edge of the secondary input signal
ICF1
ICF1IE Input Capture 1 interrupt Input capture event for CAPT1
WTIF²
ICF2
WDF
ICF2IE
WDFIE
Input Capture 2 interrupt Input capture event for CAPT2
Watchdog time-out Watchdog has timed out
interrupt
RCF
RCF
RCFIE Redundant Channel Fault Miscompare with redundant channel
interrupt
NOTES:
1 _{All flags are ORed together to generate the interrupt TCnIR.}
2 _{Only for eTimer_0.}
20.7 DMA
Each channel can request a DMA read access for each of the capture registers and a DMA write request
for each of the compare preload registers. The DREQ registers select amongst these 24 DMA request
sources to generate the 2 top level DMA request outputs.
Table 20-17. DMA Summary
DMA
Request
Channels
0-5
DMA
Enable
ICF1DE
ICF2DE
CMPLD1DE
CMPLD2DE
Name
Description
CAPT1 read request
CAPT2 read request
CMPLD1 write request
CMPLD2 write request
CAPT1 contains a value
CAPT2 contains a value
CMPLD1 needs an update
CMPLD2 needs an update
20-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor