PXS20RM Datasheet, PDF (408/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Bit number
0
1–2
3–6
Table 19-7. DMASERQ[SERQ] field structure
Description
“Set all” bit:
0 Affects only the channel specified in bit numbers 4–7
1 Affects all channels (bit numbers 4–7 are ignored)
Reserved
Set the corresponding bit in DMAERQL
19.2.1.6 eDMA Clear Enable Request (DMACERQ)
The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERQL register to disable the eDMA request for a given channel. The data value on a register write
causes the corresponding bit in the DMAERQL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAERQL to be zeroed, disabling all eDMA request inputs. If the NOP bit is set, the command is
ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all
zeroes.
See Figure 19-7 and Table 19-8 for the DMACERQ definition.
Register address: DMA_Offset + 0x0019
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CERQ
RESET:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-7. eDMA Clear Enable Request (DMACERQ) Register
Name
NOP
CERQ
Table 19-8. DMACERQ field descriptions
Description
No Operation
Clear Enable Request
Value
0 Normal operation
1 No operation, ignore the other bits in the register
See the field structure in Table 19-9
Bit number
0
1–2
3–6
Table 19-9. DMACERQ[CERQ] field structure
Description
“Clear all” bit:
0 Affects only the channel specified in bit numbers 4–7
1 Affects all channels (bit numbers 4–7 are ignored)
Reserved
Clear the corresponding bit in DMAERQL
19-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor