PXS20RM Datasheet, PDF (352/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
When in non-continuous clock mode the t_DT delay is configured according Equation 16-3. When in
continuous clock mode the delay is fixed at 1 SCK period.
16.4.3.5 Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the PCS signals to settle after a transition occurs thereby
avoiding glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPI_MCR, PCSS
provides a signal for an external demultiplexer to decode the PCS[0] -PCS[4] and PCS[6] -PCS[7] signals
into as many as 128 glitch-free PCS signals. Figure 16-22 shows the timing of the PCSS signal relative to
PCS signals.
PCSx
PCSS
t_PCSSCK
t_PASC
Figure 16-22. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected by the PCSSCK
field in the DSPI_CTAR based on the following formula:
t_PCSSCK
=
---1-----  PCSSCK
f_SYS
Eqn. 16-5
At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field
in the DSPI_CTAR based on the following formula:
t_PASC
=
----1----  PASC
f_SYS
Table 16-22 shows an example of how to compute the t_pcssck delay.
Table 16-22. Peripheral Chip Select Strobe Assert Computation Example
Eqn. 16-6
f_sys
100 MHz
PCSSCK
0b11
Prescaler
7
Delay before Transfer
70.0 ns
Table 16-23 shows an example of how to compute the t_pasc delay.
Table 16-23. Peripheral Chip Select Strobe Negate Computation Example
f_sys
100 MHz
PASC
0b11
Prescaler
7
Delay after Transfer
70.0 ns
The PCSS signal is not supported when Continuous Serial Communication SCK is enabled.
16-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor