PXS20RM Datasheet, PDF (964/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
(Nexus controllers have IDs 8 and 9, but only the last 3 bits of the ID are used for this purposes, so they
share privileges with cores 0 and 1.)
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
• Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
• Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
• Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
Writes to this word clear the region descriptor’s valid bit (see Section 30.6.4.4, MPU Region Descriptor n,
Word 3 (MPU_RGDn.Word3), for more information). Since it is also expected that system software may
adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute,
an alternate programming view of this 32-bit entity is provided. If only the access controls are being
updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n)
as stores to these locations do not affect the descriptor’s valid bit.
Offset MPU_Base + 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 15 16 17 18 19 2 21 22 23 24 25 2 27 28 29 30 31
4
0
6
R0 0 0 0 0 0 0 0M
M
M
M
3 M3S M3UM 2 M2S M2UM 1 M1S M1UM 0 M0S M0UM
P M r w xP M r w xP M r w xP M r w x
W
E
E
E
E
Reset
(n=0)
0
0
0
0
0
0
0
0
0
1
1
0
0
00
1
1
0
0
0
01
1
0
0
0
00
0
0
0
0
Reset
(n>0)
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
00
0
0
0
0
00
0
0
0
0
Figure 30-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
30-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor