PXS20RM Datasheet, PDF (663/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
25.3.3.3 Counter synchronization
Referring to Figure 25-15, the 16 bit counter will count up until its output equals VAL1 which is used to
specify the counter modulus value. The resulting compare causes a rising edge to occur on the Local Sync
signal which is one of four possible sources used to cause the 16 bit counter to be initialized with INIT. If
Local Sync is selected as the counter initialization signal, then VAL1 within the submodule effectively
controls the timer period (and thus the PWM frequency generated by that submodule) and everything
works on a local level.
VAL1
INIT
Submodule Clock
FORCE_OUT
FORCE_EN
16 bit counter
Local Sync
Master Reload
Master Sync
EXT_SYNC
0
1 Init
2
3
16 bit
comparator
Processing
Logic
Mod Compare
Master Sync
(from submod0
only)
INIT_SEL
Figure 25-15. Submodule timer synchronization
The Master Sync signal originates as the Local Sync from submodule0. If configured to do so, the timer
period of any submodule can be locked to the period of the timer in submodule0. The VAL1 register and
associated comparator of the other submodules can then be freed up for other functions such as PWM
generation, input captures, output compares, or output triggers.
The EXT_SYNC signal originates on chip or off chip depending on the system architecture. This signal
may be selected as the source for counter initialization so that an external source can control the period of
all submodules.
If the Master Reload signal is selected as the source for counter initialization, then the period of the counter
will be locked to the register reload frequency of submodule0. Since the reload frequency is usually
commensurate to the sampling frequency of the software control algorithm, the submodule counter period
will therefore equal the sampling period. As a result, this timer can be used to generate output compares
or output triggers over the entire sampling period which may consist of several PWM cycles. The Master
Reload signal can only originate from submodule0.
The counter can optionally initialize upon the assertion of the FORCE_OUT signal assuming that the
FORCE_EN bit is set. As indicated by Figure 25-15, this constitutes a second init input into the counter
which will cause the counter to initialize regardless of which signal is selected as the counter init signal.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-17