PXS20RM Datasheet, PDF (323/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
— Various programmable delays
— Programmable serial frame size of 4 to 16 bits, expandable by software control
— Programmable master bit rates
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• As many as 8 chip select lines available, depending on package and pin multiplexing
• 4 clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering as many as 5 transfers on the transmit and receive side
• Queueing operation possible through use of the eDMA
• General-purpose I/O functionality on pins when not used for SPI
16.1.3 DSPI configurations
The DSPI module on this device operates only in the SPI configuration.
16.1.3.1 SPI configuration
The SPI Configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI
to operate as a basic SPI block with internal FIFOs supporting external queues operation. Transmit data
and received data reside in separate FIFOs. The host CPU or a DMA controller read the received data from
the receive FIFO and write transmit data to the transmit FIFO.
For queued operations the SPI queues can reside in system RAM, external to the DSPI. Data transfers
between the queues and the DSPI FIFOs are accomplished by a DMA controller or host CPU. Figure 16-2
shows a system example with DMA, DSPI and external queues in system RAM.
System RAM
Addr/Ctrl
Done
RX Queue
TX Queue
Data
Data ^{DMA Controller}
Data
DSPI
Data
Addr/Ctrl
Req
TX FIFO RX FIFO
Shift Register
Figure 16-2. DSPI with queues and DMA
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-3