PXS20RM Datasheet, PDF (1042/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
UART TX buffer (FIFO mode)
Set TXEN
Enables DMA TX
channel request
(DMAERQH, DMAERQL)
!TFF & DMA_TEN
?
True
False
DMA TX transfer (Req/Ack) from
RAM area to UART TX FIFO
True
DMA TX
(major loop) done
?
False
DMA TX
(minor loop) done
?
True
False
False
!TFF
?
True
Figure 31-52. FSM to control the DMA TX interface (UART node)
The TCD settings (typical case) are shown in Table 31-48. All other TCD fields = 0. The minor loop
transfers a single byte/half-word as soon a free entry is available in the Tx FIFO.
Table 31-48. TCD settings (UART node, TX mode)
TCD Field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
SADDR[31:0]
Value
8-bit data
M
M
1
RAM address
16-bit data
2
Description
Multiple iterations for the “major” loop
Multiple iterations for the “major” loop
Minor loop transfer = 1 or 2 bytes
31-66
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor