PXS20RM Datasheet, PDF (504/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
NOTE
The FCCU Redundancy Control Checkers (RCC) should not be confused
with the Redundancy Control Checker Units (RCCU) instantiated on the
PXS20 to detect critical lockstep failure).
22.4 Signal description
The FCCU generates two external signals, FCCU_F[0] and FCCU_F[1]. These are described in
Section 22.7.10, FCCU_F interface.
22.5 Register interface
The register interface is a slave bus used for configuration purposes via the CPU.
The following bus operations are supported:
• Word (32-bit) data write/read operations to any registers
• Low and high half-words (16-bit, data[0:15] or data[16:31]) data write/read operations to any
registers
• Byte (8 bits, data[0:7] or data[8:15] or data[16:23] or data[24:31]) data write/read operations to any
registers
Any other operation (free byte enables, misaligned word or half-word access or other operations) are not
supported.
The FCCU generates a transfer error in the following cases:
• Any write/read access executed outside the address space of the peripheral
• Any write/read operation different from byte/halfword/word (free byte enables, misaligned access,
or other operations) on each register
• Any write access to the configuration registers not executed while the FCCU is not in CONFIG
state
The registers of the FCCU are accessible (read/write) in each access mode: user, supervisor, or test.
22.6 Memory map and register description
The FCCU registers are listed in Table 22-2. The contents of the configuration registers (labeled as “W in
CONFIG state only” in the Access column) can be locked by the OP16 operation as defined in the
FCCU_CTRL register.
22-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor