PXS20RM Datasheet, PDF (601/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 24
FlexCAN Module
FlexCAN Module
24.1 Introduction
The FlexCAN module is a communication controller implementing the CAN protocol according to the
CAN 2.0B protocol specification. A general block diagram is shown in Figure 24-1, which describes the
main sub-blocks implemented in the FlexCAN module, including two embedded memories, one for
storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers. This device
supports 32 Message Buffers. The functions of the sub-modules are described in subsequent sections.
MB31
RXIMR31
RXIMR30
MB30
ID Mask
Storage
128-
byte RAM
Message
Buffer
Storage
544-
byte RAM
RXIMR1
RXIMR0
MB1
MB0
Message
Buffer
Management
CAN
Protocol
Interface
max MB #
(0–31)
CAN Tx
CAN Rx
Bus Interface Unit
Freescale Semiconductor
IP Bus Interface
Clocks, Address & Data buses,
Interrupt and Test Signals
Figure 24-1. FlexCAN block diagram
PXS20 Microcontroller Reference Manual, Rev. 1
24-1