PXS20RM Datasheet, PDF (552/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Low address space
C90FL flash memory array blocks
Low address space - 256 KB
Mid address space
Mid address space - 256 KB
High address space - 512 KB
High address space
16 KB
48 KB
48 KB
16 KB
64 KB
64 KB
128 KB
128 KB
256 KB
256 KB
Figure 23-1. C90FL flash memory array diagram
23.1.2 C90FL block features
• Support for a 64-bit data bus for instruction fetch
• Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and
doubleword reads are supported. Only aligned word and doubleword writes are supported.
• Configurable read buffering and line prefetch support. Four line read buffers (128 bits wide) and a
prefetch controller are used to support single-cycle read responses for hits in the buffers.
• Hardware and software configurable read and write access protections on a per-master basis
• Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses
to proceed in parallel for interleaved or pipelined flash array designs
• Configurable access timing allowing use in a wide range of system frequencies
• Multiple-mapping support and mapping-based block access timing (0-31 additional cycles)
allowing use for emulation of other memory types
• Software programmable block program/erase restriction control for low, mid and high address
spaces
• Erase of selected block(s)
• Read page and program page size of 128 bits (4 words)
• ECC with single-bit correction, double-bit detection
23-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor