PXS20RM Datasheet, PDF (297/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

XBAR slave
port
S4
S5
S6
S7
Crossbar Switch (XBAR)
Table 15-3. XBAR slave port allocation (continued)
LSM
DPM
XBAR_0 module
—
—
—
PBRIDGE_0
XBAR_1 module
—
—
—
PBRIDGE_1
XBAR_0 module
—
—
—
PBRIDGE_0
XBAR_1 module
—
—
—
PBRIDGE_1
15.2 Introduction
15.2.1 Overview
This section provides an overview of the generic multi-layer AHB crossbar switch (XBAR¹). The purpose
of the XBAR is to concurrently support up to eight simultaneous connections between master ports and
slave ports. The XBAR supports a 32-bit address bus width and a 64-bit data bus width at all master and
slave ports.
15.2.2 Features
The XBAR has the ability to gain control of all the slave ports and prevent any masters from making
accesses to the slave ports. This feature is useful when the user wishes to turn off the clocks to the system
and needs to ensure that no bus activity will be interrupted.
The XBAR can put each slave port into a low power park mode so that slave port will not dissipate any
power transitioning address, control or data signals when not being actively accessed by a master port.
Each slave port can also support multiple master priority schemes. Each slave port has a hardware input
which selects the master priority scheme so the user can dynamically change master priority levels on a
slave port by slave port basis.
The XBAR will allow for concurrent transactions to occur from any master port to any slave port. It is
possible for all master ports and slave ports to be in use at the same time as a result of independent master
requests. If a slave port is simultaneously requested by more than one master port, arbitration logic will
select the higher priority master and grant it ownership of the slave port. All other masters requesting that
slave port will stalled until the higher priority master completes its transactions.
15.2.3 Limitations
The XBAR routes bus transactions initiated on the master ports to the appropriate slave ports. There is no
provision included to route transactions initiated on the slave ports to other slave ports or to master ports.
Simply put, the slave ports do not support the bus request/bus grant protocol, the XBAR assumes it is the
sole master of each slave port.
1.An alternate abbreviation for this module is MAX.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
15-3