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PXS20RM Datasheet, PDF (387/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller
eDMA Channel Mux (DMA_MUX)
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example,
CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit READ/WRITE to address ‘Base + 0x00’,
but performing a 32-bit access to address ‘Base + 0x01’ is illegal.
18.3.1 Register descriptions
The following memory-mapped registers are available in the DMA_MUX.
18.3.1.1 Channel Configuration Registers
Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA
slots (peripheral slots or always-on slots) in the system.
Address: Base + #n
Access: User read/write
0
1
2
3
4
5
6
7
R
ENBL
W
TRIG
SOURCE
Reset
0
0
0
0
0
0
0
0
Figure 18-2. Channel Configuration Registers (CHCONFIG#n)
Table 18-2. CHCONFIGxx Field Descriptions
Field
Description
7
ENBL
6
TRIG
5–0
SOURCE
DMA Channel Enable. ENBL enables the DMA Channel
0 DMA channel is disabled. This mode is primarily used during configuration of the DMA_MUX. The
DMA has separate channel enables/disables, which should be used to disable or re-configure a
DMA channel.
1 DMA channel is enabled
DMA Channel Trigger Enable (for triggered channels only). TRIG enables the periodic trigger
capability for the DMA Channel
0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will
simply route the specified source to the DMA channel.
1 Triggering is enabled
DMA Channel Source (slot). SOURCE specifies which DMA source, if any, is routed to a particular
DMA channel (see Section 18.4, DMA_MUX request source slot mapping).
ENBL
0
1
1
TRIG
X
0
1
Table 18-3. Channel and Trigger Enabling
Function
DMA Channel is disabled
DMA Channel is enabled with no triggering (transparent)
DMA Channel is enabled with triggering
Mode
Disabled Mode
Normal Mode
Periodic Trigger Mode
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
18-3