PXS20RM Datasheet, PDF (569/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Table 23-5. LML Field Descriptions
Field
Description
0
LME
1-10
11
SLOCK
12-13
14-15
MLOCK[1:0]
Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SLOCK, MLOCK and
LLOCK) to be set or cleared by register writes. This bit is a status bit only, and may not be written
or cleared, and the reset value is 0. The method to set this bit is to write a password, and if the
password matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset
operation occurs. For LME, the password 0xA1A1_1111 must be written to the LML register.
0 Low/Mid Address Locks are disabled, and can not be modified
1 Low/Mid Address Locks are enabled to be written
Reserved, reset to 0
Shadow Lock. This bit is used to lock the shadow block from programs and erases. A value of 1
in the SLOCK register signifies that the shadow block is locked for program and erase. A value of
0 in the SLOCK register signifies that the shadow block is available to receive program and erase
pulses. The SLOCK register is not writable once an interlock write is completed until MCR[DONE]
is set at the completion of the requested operation. Likewise, SLOCK register is not writable if a
high voltage operation is suspended. SLOCK is also not writeable during UTest operations, when
AIE is high.
Upon reset, information from the shadow block is loaded into the SLOCK register. The SLOCK bit
may be written as a register. Reset causes the bits to go back to their shadow block value. The
default value of the SLOCK bits (assuming erased shadow location) is locked.
SLOCK is not writable unless LME is high.
Reserved, reset to 0
Mid Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the
corresponding block is locked for program and erase. A value of 0 in the lock register signifies that
the corresponding block is available to receive program and erase pulses. The block numbering
for Mid Address Space starts with MLOCK[0] and continues until all blocks are accounted.
The lock register is not writable once an interlock write is completed until MCR[DONE] is set at the
completion of the requested operation. Likewise, the lock register is not writable if a high voltage
operation is suspended. MLOCK is also not writeable during UTest operations, when AIE is high.
Upon reset, information from the shadow block is loaded into the block registers. The LOCK bits
may be written as a register. Reset causes the bits to go back to their shadow block value. The
default value of the LOCK bits (assuming erased shadow location) is locked.
In the event that blocks are not present (due to configuration or total memory size), the LOCK bits
default to be locked, and are not writable. The reset value is always 1 (independent of the shadow
block), and register writes have no effect.
16-21
22-31
LLOCK[9:0]
MLOCK is not writable unless LME is high.
Reserved, reset to 0
Low Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the
corresponding block is locked for program and erase. A value of 0 in the lock register signifies that
the corresponding block is available to receive program and erase pulses. The block numbering
for Low Address Space starts with LLOCK[0] and continues until all blocks are accounted.
For more details on LLOCK, please see MLOCK bit description.
LLOCK is not writable unless LME is high.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-19