PXS20RM Datasheet, PDF (455/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
This bit inverts the OFLAG output signal polarity.
1 = Inverted polarity.
0 = True polarity.
MSTR - Master Mode
This bit enables the compare function’s output to be broadcasted to the other channels in the module.
The compare signal then can be used to reinitialize the other counters and/or force their OFLAG signal
outputs.
1 = Enable broadcast of compare events from this channel.
0 = Disable broadcast of compare events from this channel.
OUTMODE - Output Mode
These bits determine the mode of operation for the OFLAG output signal.
Table 20-7. OUTMODE Values
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Meaning
Software controlled
Clear OFLAG output on successful compare (COMP1 or COMP2)
Set OFLAG output on successful compare (COMP1 or COMP2)
Toggle OFLAG output on successful compare (COMP1 or COMP2)
Toggle OFLAG output using alternating compare registers
Set on compare with COMP1, cleared on secondary source input edge
Set on compare with COMP2, cleared on secondary source input edge
Set on compare, cleared on counter roll-over
Set on successful compare on COMP1, clear on successful compare on COMP2
Asserted while counter is active, cleared when counter is stopped.
Asserted when counting up, cleared when counting down.
Reserved
Reserved
Reserved
Reserved
Enable gated clock output while counter is active
20.4.3.10 Control Register 3 (CTRL3)
eTimer_CHNL ₀
_BASE + $12
Read
STP
Write
EN
Reset
0
1
2
3
4
5
6
7
8
9
10
ROC
0 1 1 1 1 C2FCNT[2:0]
0001111000
Figure 20-12. Control Register 3 (CTRL3)
11 12 13
C1FCNT[2:0]
000
14 15
DBGEN
[1:0]
00
STPEN - Stop Actions Enable
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-13