PXS20RM Datasheet, PDF (930/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
corresponding CLRx bit and then writes ‘1’ to a SETx bit on the first processor, informing it that it now
can access the block of data.
28.6.9 Lowering Priority Within an ISR
In SoC implementations without the software settable interrupt requests in Section 28.4.7, INTC Software
Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7), the only other way besides
scheduling a task through an RTOS to not have priority inversion with an ISR whose work spans multiple
priorities as described in Section 28.6.8.1, Scheduling a Lower Priority Portion of an ISR, is to lower the
current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in either Section 28.4.4, INTC Current Priority
Register for Processor 0 (INTC_CPR_PRC0), within an ISR to below the
ISR’s corresponding PRI value in Section 28.4.8, INTC Priority Select
Registers (INTC_PSR0_3 - INTC_PSR252_255), allows more preemptions
than the depth of the LIFO can support.
Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid priority
inversion.
28.6.10 Negating an Interrupt Request Outside of its ISR
28.6.10.1 Negating an Interrupt Request as a Side Effect of an ISR
Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits, and consequently their
corresponding interrupt requests too. This clearing as a side effect of servicing a peripheral interrupt
request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request
whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be
a desired effect.
28.6.10.2 Negating Multiple Interrupt Requests in One ISR
An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears multiple flag bits
is because it serviced those other flag bits, and therefore the ISRs for these other flag bits do not need to
be executed.
28.6.10.3 Proper Setting of Interrupt Request Priority
Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR execution or
the intentional clearing a flag bit, the priorities of the peripheral or software settable interrupt requests for
these other flag bits must be selected properly. Their PRIx values in Section 28.4.8, INTC Priority Select
Registers (INTC_PSR0_3 - INTC_PSR252_255), must be selected to be at or lower than the priority of
the ISR that cleared their flag bits. Otherwise, those flag bits still can cause the interrupt request to the
processor to assert. Furthermore, the clearing of these other flag bits also has the same timing relationship
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor