PXS20RM Datasheet, PDF (476/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Table 21-1. ECSM memory map (continued)
ECSM offset
Register
0x0004
0x0008
0x000C
0x0010–
0x0023
0x0024
0x0028
0x002C -
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
0x0070 -
0x007C
Platform Crossbar Master Configuration (PLAMC) Platform Crossbar Slave Configuration (PLASC)
IPS On-Platform Module Configuration (IOPMC)
Reserved
Misc Reset Status
(MRSR)
Reserved
Miscellaneous User-Defined Control Register (MUDCR)
Reserved
Reserved
Reserved
ECC Configuration
(ECR)
Reserved
ECC Status
(ESR)
Reserved
ECC Error Generation (EEGR)
Reserved
Platform Flash Memory ECC Address (PFEAR)
Reserved
Platform Flash Memory Platform Flash Memory
ECC Master
ECC Attributes
(PFEMR)
(PFEAT)
Platform Flash Memory ECC Data High (PFEDRH)
Platform Flash Memory ECC Data Low (PFEDRL)
Platform RAM ECC Address (PREAR)
Reserved
Platform RAM ECC
Syndrome
(PRESR)
Platform RAM ECC
Master
(PREMR)
Platform RAM ECC
Attributes
(PREAT)
Platform RAM ECC Data High (PREDRH)
Platform RAM ECC Data Low (PREDRL)
Reserved
21.4.2 Register description
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
21-2
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor