PXS20RM Datasheet, PDF (473/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
operation of the capture circuits is the arming logic which allows captures to be performed in a free running
(continuous) or one shot fashion. In free running mode, the capture sequences will be performed
indefinitely. If both capture circuits are enabled, they will work together in a ping-pong style where a
capture event from one circuit leads to the arming of the other and vice versa. In one shot mode, only one
capture sequence will be performed. If both capture circuits are enabled, capture circuit 0 is first armed
and when a capture event occurs, capture circuit 1 is armed. Once the second capture occurs, further
captures are disabled until another capture sequence is initiated. Both capture circuits are also capable of
generating an interrupt to the CPU.
20.5.3.4 Master/Slave Mode
Any timer channel can be assigned as a Master (MSTR = 1). A Master’s compare signal can be
broadcasted to the other channels within the module. The other counters can be configured to reinitialize
their counters (COINIT = 1) and/or force their OFLAG output signals (COFRC = 1) to predetermined
values when a Master counter compare event occurs.
20.5.3.5 Watchdog Timer
The watchdog timer is used to monitor for a stalled count when channel 0 is in quadrature count mode.
When the watchdog is enabled, it loads the time-out value into a down counter. The down counter counts
as long as channel 0 is in quadrature decode count mode. If this down counter reaches zero, an interrupt
is asserted. The down counter is reloaded to the time-out value each time the counter value from channel
0 changes. If the channel 0 count value is toggling between two values (indicating a possibly stalled
encoder), then the down counter is not reloaded.
20.6 Interrupts
Each of the channels within the eTimer can generate an interrupt from several sources. The watchdog and
the fault logic also generate interrupts. The interrupt service routine (ISR) must check the related interrupt
enables and interrupt flags to determine the actual cause of the interrupt.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-31