PXS20RM Datasheet, PDF (250/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Cross-Triggering Unit (CTU)
• Sequential mode: each event source for the incoming signals can generate one trigger event
output, the next event source generates the next trigger event output, and so on in a predefined
sequence. For the ADC, a commands list is entered by the CPU and the sequence of the selected
incoming trigger events generate commands or stream of commands.
The TGS Mode is selected using the TGS_M bit in the TGS Control Register.
13.4.4 TGS in triggered mode
The structure of the TGS in Triggered Mode is shown in Figure 13-3.
CTU Clock (as PWM)
PWM_REL
PWM_ODD_x
PWM_EVEN_x
RPWM_x
TGS Counter Compare Register TGS Counter Comparator
TGS Counter STOP Signal
Prescaler (1, 2, 3, 4)
TGS Counter
TGS Counter Reload Register
ETIMER0_IN
ETIMER1_IN
EXT_IN
OR
Triggers Compare Registers
(double-buffered)
Comparators
Input Selection
32-bit Register
Master Reload Signal (MRS)
Figure 13-3. TGS in triggered mode
The TGS has 16 input signals, each of which is selected from the input selection register (TGSISR),
selecting the states inactive, rising, falling or both. Depending on the selection, up to 32 input events can
be enabled. These signals are OR-ed in order to generate the MRS. The MRS, at the beginning of the
control cycle "N” (defined by the MRS occurrence), is used to pre-load the TGS counter register, using the
pre-load value written into the double-buffered register (TGSCRR), during the control cycle "N-1”, and to
reload all the double-buffered registers (Trigger Compare registers, TGSCR, TGSCRR itself etc).
The triggers list registers, consist of 8 compare registers. Each triggers list register is associated with a
comparator. On reload (MRS occurrence), the comparators are disabled: 1 TGS clock cycle is necessary
to enable them and to start the counting. The MRS is output together with individual trigger signals. The
MRS can be performed by hardware or by software. The MRS_SG bit in the CTU control register, if set
to 1, generates equivalent software MRS (i.e. resets/reloads TGS Counter and reloads all double-buffered
registers). This bit is cleared by each hardware or software MRS occurrence.
The TGS counter compare register and the TGS counter comparator, are used to stop the TGS counter
when it reaches the value stored in the TGS counter compare register, before an MRS occurs.
13-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor