PXS20RM Datasheet, PDF (350/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
The POPNXTPTR field in the DSPI_SR points to the RX FIFO entry that is returned when the
DSPI_POPR is read. The POPNXTPTR contains the positive offset from DSPI_RXFR0 in number of
32-bit registers. For example, POPNXTPTR equal to two means that the DSPI_RXFR2 contains the
received SPI data that will be returned when DSPI_POPR is read. The POPNXTPTR field is incremented
every time the DSPI_POPR is read. The maximum value of the field is equal to DSPI_HCR[RXFR] and
it rolls over after reaching the maximum.
16.4.2.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to
the RX FIFO the RX FIFO Counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI_SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI_MCR, the data from
the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the incoming data is
ignored.
16.4.2.5.2 Draining the RX FIFO
Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the DSPI POP RX FIFO
Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO Counter by one. Attempts to
pop data from an empty RX FIFO are ignored and the RX FIFO Counter remains unchanged. The data,
read from the empty RX FIFO, is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the DSPI_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the DMA controller indicates that a read from DSPI_POPR is
complete or by writing a ‘1’ to it.
16.4.3 DSPI baud rate and clock delay generation
The SCK frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option for doubling the baud rate. Figure 16-21 shows
conceptually how the SCK signal is generated.
System Clock
1
Prescaler
1+DBR
Scaler
SCK
Figure 16-21. Communications clock prescalers and scalers
16.4.3.1 Baud rate generator
The Baud Rate is the frequency of the Serial Communication Clock (SCK). The system clock is divided
by a prescaler (PBR) and scaler (BR) to produce SCK with the possibility of halving the scaler division.
The DBR, PBR and BR fields in the DSPI_CTARs (see Section 16.3.2.4, DSPI Clock and Transfer
16-30
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor