PXS20RM Datasheet, PDF (338/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Address: DSPI_BASE + 0x2C
0
1
2
3
4
5
6
7
8
R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0
W w1c w1c
w1c w1c
w1c
Reset 0 0 0 0 0 0 0 0 0
Access:
9
10
11
12
13
14
15
0 SPEF 0 RFOF 0 RFDF 0
w1c
w1c
w1c
0 000000
16
R
W
Reset 0
17
18
19
20 21 22 23 24 25
26
27
28
29
30
31
TXCTR
TXNXTPTR
RXCTR
POPNXTPTR
0 0 0 0 0 0 00 0 0 0 0 0 0 0
Figure 16-11. DSPI Status Register (DSPI_SR) for cut2/3
Field
TCF
TXRXS
EOQF
TFUF
TFFF
Table 16-11. DSPI_SR field descriptions
Description
Transfer Complete Flag. A value of TCF = 1 indicates that at least one serial-data-word (frame) from
the FIFO has been transferred/received over the serial link. For example, if after 4 transfer words are
written, then TCF would be set after the first word has been completely transferred.
0 Transfer not complete
1 Transfer complete
Note: It is recommended not to write this bit when the transfer is occurring, since the update from the
serial-link side has a higher priority than the register access. In other words, register access is
ignored if it occurs in the same clock cycle as the completion of any serial transfer.
TX & RX Status. The TXRXS bit reflects the run status of the DSPI. See Section 16.4.1, Start and
Stop of DSPI Transfers, what causes this bit to be set or cleared.
0 TX and RX operations are disabled (DSPI is in STOPPED state)
1 TX and RX operations are enabled (DSPI is in RUNNING state)
End of Queue Flag. The EOQF bit indicates that the last entry in a queue has been transmitted when
the DSPI in the master mode. The EOQF bit is set when TX FIFO entry has the EOQ bit set in the
command halfword (DSPI Push Tx FIFO) and the end of the transfer is reached. The EOQF bit
remains set until cleared by writing 1 to it. When the EOQF bit is set, the TXRXS bit is automatically
cleared.
0 EOQ is not set in the executed command
1 EOQ bit is set in the executed SPI command
Note: EOQF does not function in slave mode.
Transmit FIFO Underflow Flag. The TFUF bit indicates that an underflow condition in the TX FIFO has
occurred. The transmit underflow condition is detected only for DSPI blocks operating in slave mode
and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode
is empty, and a transfer is initiated by an external SPI master. The TFUF bit remains set until cleared
by writing 1 to it.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
Transmit FIFO Fill Flag. The TFFF bit provides a method for the DSPI to request more entries to be
added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared
by writing 1 to it or by acknowledgement from the DMA controller to the TX FIFO full request.
0 TX FIFO is full
1 TX FIFO is not full
16-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor